In broadband networks, signals are transmitted between components in the networks, such as computer networks, communication networks, and the like. The components in a network may have exposed interfaces that subject the network to electrostatic discharging (ESD) currents, which are caused by the discharging of electrostatic charges. The ESD currents may reach very high levels in a very short period of time, and hence have the potential to destroy the components in the network. Accordingly, ESD protection circuits are designed to protect the components in the network from the ESD currents.
FIG. 1 illustrates a conventional network formed on a printed circuit board (PCB). A transmitter, which is a semiconductor chip comprising integrated circuits, sends data to a receiver, which may be another semiconductor chip comprising integrated circuits. The data are transmitted through a channel on the PCB. To protect the transmitter and the receiver, diodes D are formed in the semiconductor chips as ESD devices. If an ESD transient occurs, for example, on pins A or pins B of the semiconductor chips, diodes D may be activated to conduct the ESD currents, and hence terminating circuit TX and receiving circuit RX are protected.
The circuit shown in FIG. 1 suffers from drawbacks. Since the package traces, the channels on a PCB and diodes D have parasitic capacitances. These parasitic capacitances form low-pass filters that limit the bandwidth of the network, particularly at high frequencies. Therefore, the frequency of the network as shown in FIG. 1 is limited to about 5 GHz to about 6 GHz. However, modern data networks often require frequencies up to 10 GHz or even higher. The conventional network can thus no longer meet the bandwidth requirement of the modern data networks.
To solve the above-discussed bandwidth limiting problems, a solution as shown in FIG. 2 was proposed. In this solution, two T-coils are used in the network to provide inductance for compensating for the input impedance. FIG. 3 illustrates a T-coil, which is formed of coiled metal lines. The T-coil has terminals A, B, and X (hence the name T-coil), wherein terminal X is a central tap. Referring back to FIG. 2, inductors T1A and T1B belong to a first T-coil, wherein points A1, B1 and X1 are the terminals of the first T-coil. Inductors T2A and T2B belong to a second T-coil, wherein points A2, B2 and X2 are the terminals of the second T-coil. The inductances of inductors T1A, T1B, T2A, and T2B compensate for the parasitic capacitance caused by the package/trace, the bond pads and ESD diodes D, and hence the bandwidth of the network is improved.
The network shown in FIG. 2, however, also suffers from drawbacks. Current I shown in FIG. 2 illustrates a possible ESD current path. Since ESD currents need to flow through inductors T1A and T2A (which are portions of the T-coils), the T-coils need to be thick and wide enough so that the inductors with minimized resistances are not damaged by the ESD currents, which may be very high. As a result, the T-coils need to be formed in multiple metal layers or have great metal widths to satisfy the demanding resistance requirement. This requires the T-coils to occupy more chip area or to use lower metal layers. However, larger T-coils result in greater parasitic capacitances to be introduced, and hence the improvement to the bandwidth is limited. Accordingly, a new ESD circuit with improved bandwidth and reduced chip area usage is needed.